Cadence New Library Support For Arm

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Cadence Design Systems recently announced that Arm will now utilise Cadence Liberate MX Trio Characterisation to improve and enhance the quality of the embedded memory instances and compilers. With the Liberate MX Trio Characterisation, Arm has seen better accuracy and capacity requirements and reduced memory liberty variation format (LVF) characterisation validation runtime by up to 7 times when compared to brute-force Monte Carlo simulations.

“Arm has been leveraging the Liberate Trio Characterisation Suite for standard cell characterisation, so it was an easy choice for us to broaden our deployment with Liberate MX Trio Characterisation to address our evolving LVF memory characterisation needs,” said Philippe Moyer, VP of Design Enablement, Physical Design Group, Arm. “By incorporating Liberate MX Trio Characterisation into our methodology, we are improving accuracy, capacity and meeting time-to-market goals with the delivery of our embedded memory instances and compilers.”

“Memory characterisation can have a significant impact on signoff accuracy, and Arm was looking for a reliable solution for its embedded memory IP that would help them achieve their accuracy requirements while speeding time to market,” said Sharad Mehrotra, VP of R&D, in the Digital & Signoff Group at Cadence. “Arm joined a community of successful, production-proven Liberate MX Trio Characterisation customers, trusting the solution for its memory characterization needs and expanding upon its use of the broader Liberate product portfolio for standard cell power and performance characterisation.”

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Liberate MX Trio characterisation is a library characterisation solution that is designed for large, advanced node memory designs that can enable the Arm engineers to perform characterisation validation of embedded memory instances and compilers efficiently and accurately. Liberate MX Trio Characterisation has provided Arm with automated and simulation-based dynamic partitioning to reduce runtime, improve capacity and maintain SPICE-level performance and accuracy. Simulations on the full RC netlist covering a complete vector set let Arm identify accurate worst-case paths and maintain SPICE-level accuracy.


 

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