Anritsu to Host Educational Test Talks During DesignCon in San Jose

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Anritsu will host a series of Anritsu Test Talks on Wednesday, August 18 during DesignCon, the premier high-speed communications and system design conference. The full day of education and live demonstrations will provide chipset, board, and system design engineers with insights on emerging high-speed technologies, including PCIe® 5.0 and 6.0, and effective test processes to ensure design performance. 

All the sessions will be held in Room 210F of the San Jose McEnery Convention Center. Experienced engineers with expertise in the respective technologies will lead each session conducted by Anritsu, a DesignCon Diamond Sponsor.  

Seven Educational Sessions and Demonstrations

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Seven Anritsu Test Talks will be conducted from 9:00 a.m. to 5:00 p.m. on Wednesday, August 18. The sessions range from 40-60 minutes. Synopses of the Test Talks are: 

Importance of Sequential Peeling Extraction and De-embedding When Designing PCBs

Time: 9:00 am – 9:40 am

Abstract: Engineers designing and testing differential devices, particularly printed circuit boards (PCBs), rely on vector network analyzers (VNAs) to shorten design cycles and speed time-to-market. As designs extend to higher frequencies and board space is at a premium, specific VNA tools and test techniques gain importance. Attendees will learn about these approaches, including sequential peeling extraction and de-embedding.

Open House for PCIe 5.0 RX LEQ Test Live Demo 

Time: 10:00 am – 11:00 am (Attendees can visit any time during the hour)

Abstract: Live PCIe 5.0 LEQ tests using a real Generation 5 (G5) device under test (DUT) will be conducted. Visitors will experience the test procedure of G5 LEQ test using the Anritsu Signal Quality Analyzer-R MP1900A. 

AM4 BER and JTOL Test Solution for PCIe 6.0 and Beyond

Time: 11:05 am – 11:45 am

Abstract: This session will provide an overview of 32 Gbaud and above, PAM4 BER test, and Jitter tolerance (JTOL) measurements. It will also include Forward Error Correction (FEC) and burst errors analysis. Engineers involved in PCIe 6.0 or 400GE/800GE applications will find this session highly informative.

Live Demo of PAM4 BERT and JTOL, FEC and Burst Error Analysis

Time: 12:00 pm – 12:45 pm

Abstract: Attendees will see a live demonstration of PAM4 JTOL test and FEC burst error analysis using the MP1900A. The demo will show:

  • PAM4 BERT Product Overview and Capabilities
  • PAM4 BER and Jitter Tolerance Test
  • FEC Burst Error Capture and Analysis

Automotive Test Solutions 

Time: 2:00 pm – 2:40 pm

Abstract: This session will provide an overview of Anritsu test solutions for automotive. Among the technologies and applications to be discussed are 5G/cellular, infotainment/connectivity/Bluetooth® /WLAN, ADAS, RADAR, C-V2X, and PCIe.

USB Type-C Standard PHY testing. What’s the same, and what’s different?
Time: 3:00 pm – 3:40 pm

Abstract: USB4 and DisplayPort have adopted Intel’s Thunderbolt PHY specification as a “building block” at the physical layer. This session will discuss the similarities and differences between these standards as related to Compliance Test Specifications (CTS) and test methodologies.

PCIe 5.0 Receiver LEQ Compliance Test

Time: 4:00 pm – 5:00 pm

Abstract: Attendees of the final Anritsu Test Talk will learn about the methods to solve new test and measurement receiver challenges for PCIe 5.0 at 32.0 GT/s. Topics to be covered include:

  • PCI-SIG® 5.0 compliance program
  • Challenges and latest guidelines on 32 GT/s receiver testing
  • Nuances of the 32 GT/s stressed eye calibration and handling high loss backchannels with equalization
  • Solving validation challenges with a receiver solution

The educational sessions are free and open to all DesignCon attendees.

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