TSMC’s N3 Process: Cadence Digital and Custom Flows Achieve Certification

Image Source - Taiwan Semiconductor Manufacturing Company

Cadence and TSMC have broadened collaboration to continue advancing mobile, AI and hyperscale electronics innovation

Cadence Design Systems’ digital full flow and custom tool suite has been optimized for TSMC’s 3nm (N3) process technology. The Cadence tools, as the company infomred, have achieved the latest Design Rule Manual (DRM) and SPICE certification for TSMC’s N3 process.

“By continuing to extend our collaboration with Cadence, we’re providing support for our customers that are designing the next generation of mobile, AI and HPC systems using our latest N3 process,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC.

“We’ve continued to work closely with TSMC to enable our customers to take advantage of the most advanced technologies required to support today’s emerging mobile, AI and HPC applications,” said Dr Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence.

Downloadable corresponding N3 process design kit

The Cadence team has put up the corresponding N3 process design kit on its website for download for its customers. It comes updated and certified for use on TSMC’s N3 process technology. It features enhanced physical optimization and timing signoff closure.

“It includes the Innovus Implementation System, Liberate Characterization, Liberate Variety Statistical Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus Verification System. Additionally, the Genus Synthesis Solution and its predictive iSpatial technology is enabled for these process technologies for mobile, AI and hyperscale designs,” read company’s official statement.

Custom enhancements for TSMC’s N3 process technology also include expanded 3nm design rule support, custom digital color remastering, enhanced analog cell support, additional productivity improvements with an enhanced device-level P&R flow and a front-to-back legacy-node design migration flow.

“Our latest work enables our customers to design with the tools, benefitting from the significant power and performance boost of TSMC’s 3nm process technology and to quickly launch their new product innovations to market,” added Lee.

Teng stated, “Based on latest N3 certification from TSMC and our joint successes with customers on N7 and N5 designs, customers are now evaluating our digital reference flow on TSMC’s N3 process technology to take their designs to the next level.”


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