UK-based Imperas Software recently announced the release of the first open-source SystemVerilog RISC-V processor library which will be specifically designed for functional coverage library for RISC-V cores. The latest release is intended for RV32IMC, RV64 and other ratified extensions which are under development, and it will also be released as part of the riscvOVPsimPlus which is a package with a free-to-use permission license from Imperas, which covers commercial and academic use.
The development of the instruction level SystemVerilog coverage library needs an understanding of the verification process and general requirements of the design verification community.
“Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture,” said Allen Baum of Esperanto Technologies, and Chair of the RISC-V International Architecture Test SIG. “The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.”
“The open standard ISA of RISC-V provides great flexibility for innovation in the design of modern processor implementations,” said Simon Davidmann, CEO at Imperas Software. “With all the configurability offered by the standard extensions and implementation options, plus users-defined custom features, the total scope of the RISC-V verification effort cannot be understated. Through our experience working with some of the most sophisticated customer designs, we recognise the usefulness of ready-to-use SystemVerilog Verification IP that allows developers a solid foundation on which to build a successful DV plan.”
Imperas had hitherto developed these libraries over time to provide support for multiple customer projects and customers of the Imperas commercial tools, such as ImperasDV. Nevertheless, with the rapid growth in the take-up rates and many new groups now developing a complex RISC-V processor DV task for the first time, the emerging RISC-V verification community has an immediate need for qualified Verification IP from a dependable source.
