Centre May Revise Chip DLI Norms: Rajeev Chandrasekhar

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He also said the scheme will continue to be in place to support all product design projects and start-ups, among others

The Centre is mulling revising the mandates of the Rs 76,000 crore design linked incentive (DLI) program after receiving feedback on the policy during the SemiCon India conference 2022 held in Bangalore, Minister of State for Electronics and IT Rajeev Chandrasekhar.

He was addressing the media at the conference after seven memorandums of understanding (MoUs) were signed between government organisations and technology companies.

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“Whether the DLI norms need to be modified… We have got some feedback from this conference that maybe the DLI has been designed to be very narrow. Maybe there is a cap on funding that is too restrictive. We will examine all that,” Chandrasekhar told reporters.
He also said the scheme will continue to be in place to support all product design projects and start-ups, among others.

“I want to say this very clearly that the USD 10 million package of the Rs 76,000 crore package is for the ecosystem and design and innovation is a very important part of the ecosystem. Talent is a very important part of the ecosystem. There is a need to sort of redesign some of those pieces, we will do it,” Chandrasekhar said.

The scheme provides for reimbursement of up to Rs 30 lakh per application for MPW (multi-project wafer) fabrication of design and post-silicon validation activities; reimbursement of up to 50 per cent of the eligible expenditure subject to a ceiling of Rs 15 crore per application for designing semiconductor goods; and reimbursement of 6 to 4 per cent of net sales of designed semiconductor goods over 5 years subject to a ceiling of Rs 30 crore.

At the event, the Ministry of Electronics and IT announced the onboarding of Prof Rao Tummala from Georgia Tech University, US, on the Advisory Committee of India Semiconductor Mission.

MoUs were signed between Cyient, WiSig Networks and IIT Hyderabad to enable mass production of “5G Narrowband-IoT- the Koala Chip, Architected and Designed in India”.
Signalchip Innovations, Ministry of Electronics and IT (MeitY) and the Centre for Development of Advanced Computing (C-DAC) signed an agreement for not only design and manufacture but also deployment and maintenance of 10 lakh Integrated NavIC (Navigation with Indian Constellation) and GPS Receivers.

Besides, Semiconductor Research Corporation (SRC) USA and IIT Bombay will focus on bringing together SRC’s industry experts and India’s R&D talent to create an industry driven research and development program.

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