Surface mount technology (SMT) packaging is a highly important part in the overall manufacturing process. However, India still has a long way to go in terms of reaching the advanced stage of SMT packaging. There are a number of technicalities involved in SMT packaging like providing power to the silicon and keeping it cool. In every package, heat plays an integral part because if heat is not adequate, temperature will slow the electrons down.
By Jesus Milton Rousseau S
Monday, November 16, 2009: “Some people say that SMT packaging is the tapes/stick/trays meant to put surface mount devices (SMD). But in semiconductors parlance packaging means attaching and wire bonding the die inside the SMD package (for example, SOIC, QFP, QFN, BGA) etc”, says Alok Gupta, director, Prosem Technology.
Different types of packaging
With new technologies evolving by the day, more challenges are being faced by designers and engineers to ensure optimum usage of packages. To achieve the highest performance, the package must be deleted and bare silicon must be used. But that will not be easy for the engineers who deal with mounting bare silicon on motherboards. The terms used for mounting bare silicon are chip-onboard (COB), flip chip and direct chip attach (DCA). Each term represents a different process. COB is used when the silicon is either wire-bonded to the board directly or is used in the form of tape-automated bonding (TAB). However, chip, wire and TAB add wire-bond inductance similar to the package. Highest performance is achieved when the bare silicon is flipped directly over and bonded to the underlying substrate. No wire bonds or leads are involved in the flip chip process.
Another innovative concept in the packaging industry has been the wafer format. Several companies have started offering devices processed and packaged in wafer-format. This concept involves the creation of a redistribution layer over the face of the chip. Wafer packaging can transform IC packaging from a labour-intensive process involving making wire bonds one-at-a-time on individual dye, to a batch process, much like wafer fabrication.
What’s new in packaging
Novacap, a Dover company, has introduced the cap rack series of component arrays that combine a custom selection of individual ceramic components into a single surface mount package. “Components in each cap rack array can consist of highly matched multi-layer ceramic capacitors (MLCCs) and/or a combination of MLCCs with dissimilar capacitance values and dielectrics. They also can be configured to include other passive devices (ceramic resistors and inductors). CR assemblies are particularly suited to high-reliability applications including implanted medical devices and military, aerospace, space and high-end telecom equipment,” adds Sudhakar, country manager, Ceramic and Microwave Products, Dover Electronics.
Key features of cap rack series include negligible cross talk, that is, components are separated by high temperature epoxy to minimise coupling. It offers the choice of passive component combinations, meaning the designers can choose capacitors of the same dielectric type with precise capacitance matching or capacitors of different dielectric types, as well as other passive component types (inductors, resistors). The other features are board process efficiency improvements, that are multiple component placements in a single processing step; and unique chip orientation reduces board area by utilising smaller chip pads compared to standard single-chip placement. And there is MIL PRF screening, an option where individual components can be screened prior to assembly.
Different packages on SMD
The most common SMD packaging available for multiple lead include small outline (SO), quad flat pack (QFP), plastic leaded chip carrier (PLCC), tape automated bonding (TAB), and leadless ceramic chip carrier (LCCC) packaging. And the three lead configurations most commonly used with SM packages are the gull-wing, J-lead and I lead. Surface-mount components are usually smaller than their counterparts with leads and are designed to be handled by machines rather than by humans. The electronics industry has standardised package shapes and sizes.
But there are often subtle variations in package details from manufacturer to manufacturer, and even though standard designations are used, designers need to confirm dimensions when laying out printed circuit boards.
SMD components used inSMT machines
“SMD can be split into a number of categories like passive SMDs, transistors and integrated circuits. A number of different packages are used for passive SMDs. However, the majority of passive SMDs are either resistors or capacitors for which the package sizes are reasonably standardised. Other components including coils, crystals and others tend to have more individual requirements and hence their own packages,” says M Anil Kumar, director, SLN Technologies.
Resistor and capacitor packages have a variety of packages. These have designations that include: 1812, 1206, 0805, 0603, 0402, and 0201. In other words the 1206 measures 1200 by 600 of an inch. The larger sizes such as 1812 and 1206 were some of the first that were used. They are not widely used now as much smaller components are generally required. However, they may find use in applications where larger powers are needed or where other considerations require the larger size. The connections to the PCB are made through metallised areas at either end of the package.
Transistors and diodes are often contained in a small plastic package. The connections are made via leads which emanate from the package and are bent so that they touch the board. Three leads are always used for these packages. In this way it is easy to identify which way round the device must go.
In integrated circuits, there is a variety of packages which are used. The package used depends upon the level of interconnectivity required. Many
chips like the simple logic chips may only require 14 or 16 pins, whereas other like the VLSI processors and associated chips can require up to 200 or more. In view of the wide variation of requirements there is a number of different packages available. For the smaller chips, packages such as the small outline integrated circuit (SOIC) may be used. These are effectively the SMT version of the familiar Dual in line (DIL) packages used for the familiar 74 series logic chips. Besides, there are smaller versions including TSOP (thin small outline package) and Shrink small outline package (SSOP). The VLSI chips require a different approach. Typically a package known as a quad flat pack (QFP) is used. This has a square footprint and has pins emanating on all four sides. Pins again are bent out of the package in what is termed a gull-wing formation so that they meet the board. The spacing of the pins is dependent upon the number of pins required. For some chips it may be as close as 20 thousandths of an inch. Great care is required when packaging these chips and handling them as the pins are very easily bent.
Other packages are also available. One known as a ball grid array (BGA) is used in many applications. Instead of having the connections on the side of the package, they are underneath. The connection pads have balls of solder that melt during the soldering process, thereby making a good connection with the board and mechanically attaching it. As the whole of the underside of the package can be used, the pitch of the connections is wider and it is found to be much more reliable.
How components are packaged
Today, most active components are available in surface mount. The most common is tape and reel. It requires fewer machine reloads allowing more machine run time. Trays are also used, generally for large packages such as QFP. There are standardised reel specifications for passive components and active components. “The smaller components are packaged in tape or reel forms and bigger components are packaged in trays, for example the larger ICs. Today majority of the surface mount components are imported from abroad,” adds Subhash Goyal, MD, Digital Circuits Pvt Ltd.
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